搜索资源列表
lab5
- Verilog 程序 可以实现带进位的8bit加法和减法-The Verilog procedures can achieve 8bit addition and subtraction with carry
add_tree
- 加法树的源代码，是乘法和除法的基础，也即数字电路的verilog基础代码，已经仿真过，完全正确-Adder tree source code, multiplication and division, digital circuit verilog code base simulation entirely correct
BCD
- 利用Verilog HDL语言实现BCD码的加法-Using Verilog HDL language implementation of BCD addition
jianyijiafaqi
- 采用MAX+PlusII工具编辑设计的Verilog程序设计的简易加法器。可实现10以内的加法计算-Using MAX+PlusII tools to edit the design of Verilog design of a simple adder. Can be realized within 10 addition calculation
verilog_stand_cell_lib
- verilog 门级设计及仿真标准单元库，包含142个基本的逻辑门单元。可用于VERILOG开发实现与或非、加法、减法、累加等基本的逻辑运算单元，实现精确的逻辑仿真。-verilog gate-level design and simulation of a standard cell library contains 142 basic logic gate unit. VERILOG implementation and can be used to develop or, addition
carry_skip_adder_verilog
- 行波加法器能对两个n位数的各位同时进行加法运算的装置,可由n个一位加法器(全加器)并联而。本程序是它的verilog实现-Line wave and instruments capable of two n-digit device you carry adder, while the n by an adder (full adder) in parallel while. This program is to achieve its verilog
Float_add
- 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
YSW
- 基于FPGA的使用VERILOG语言编写的四联十进制加法的程序-Decimal addition quadruple
add16
- 基于FPGA的VERILOG语言的四联十六进制的加法程序-Based on quadruple hexadecimal addition program the FPGA VERILOG language
fullAdder32
- 阵列加法器,实现加法功能，快速加法的功能，verilog代码-Array adder adding function to achieve rapid addition of features, verilog code
count15
- 用verilog语言实现15进制加法计数器的功能-Achieve 15 binary adder counter function using verilog language
count_1000
- 适用于verilog hdl初学者——0-999加法计数器，内带vwf波形仿真-Suitable for beginners 0-999 adding counter verilog hdl, which with vwf waveform simulation
Verilog_add_div_multi_exp
- 使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.
adder_32bits
- 采用“进位选择加法”技术设计32位加法器 Verilog语言编写-32 bit adder
counter
- 用verilog语言实现计数器设计，其中包括同步加法计数器、同步减法计数器、异步加法、异步减法-Design verilog language implement counter
counter
- Verilog语言编写的8进制同步、异步加法计数器-Verilog language octal synchronous, asynchronous addition counter
floatadd
- 32位浮点数加法，使用的语言是verilog。其中包括的是工程中的v文件。-32-bit floating-point addition, the use of language is verilog. Including is v of the engineering documents.